;*******************************************************************************
;   MSP430xG461x Demo -  DMA0, Rpt'd Block, I2C Master Intf. to DAC8571, DCO
;   Master = MSP430F4619, Slave = DAC8571
;
;   Description: Using the DMA0, 16-bit sine data is transmitted to the
;   external DAC. The DAC8571 is configured and sent continuous data without
;   a stop or repeated start condition. Data is handled in bytes by the I2C
;   module and the CPU is normally in LPM0.
;   ACLK = 32kHz, MCLK = SMCLK = TACLK = BRCLK = 1MHz
;
;                MSP430xG461x                       DAC8571
;            ------------------                   ------------
;          -|XIN   P3.1/UCB0SDA|<--------------->|SDA         |
;     32kHz |      P3.2/UCB0SCL|---------------->|SCL  I2C    |
;          -|XOUT              |                 |    SLAVE   |
;           |     I2C MASTER   |              GND|A0          |
;
;
;   DAC8571 I2C address = 0x4C (A0 = GND)
;
;   A. Dannenberg/ K.Venkat
;   Texas Instruments Inc.
;   Dec 2006
;   Built with IAR Embedded Workbench Version: 3.41A
;*******************************************************************************
#include "msp430xG46x.h"
;-------------------------------------------------------------------------------
            RSEG    CSTACK                  ; Define stack segment
;-------------------------------------------------------------------------------
            RSEG    CODE                    ; Assemble to Flash memory
;-------------------------------------------------------------------------------
RESET       mov.w   #SFE(CSTACK),SP         ; Initialize stackpointer
StopWDT     mov.w   #WDTPW+WDTHOLD,&WDTCTL  ; Stop Watchdog Timer
SetupP3     bis.b   #06h,&P3SEL             ; Assign I2C pins to USCI_B0
SetupUCB0   bis.b   #UCSWRST,&UCB0CTL1      ; Enable SW reset
            mov.b   #UCMST+UCMODE_3+UCSYNC,&UCB0CTL0
                                            ; I2C Master, synchronous mode
            mov.b   #UCSSEL_2+UCSWRST,&UCB0CTL1
                                            ; Use SMCLK, keep SW reset
            mov.b   #11,&UCB0BR0            ; fSCL = SMCLK/11 = 95.3kHz
            mov.b   #00,&UCB0BR1
            mov.w   #04ch,&UCB0I2CSA        ; Set slave address
            bic.b   #UCSWRST,&UCB0CTL1      ; Clear SW reset, resume operation
SetupDMA    mov.w   #DMA0TSEL_13,&DMACTL0   ; USCI_B0 Transmit Ready Trigger
            movx.a  #Sine_Tab,&DMA0SA       ; Source block address
            movx.a  #UCB0TXBUF,&DMA0DA      ; Destination single address
            mov.w   #020h,&DMA0SZ           ; Block size
            mov.w   #DMADT_4+DMASRCINCR_3+DMADSTBYTE+DMASRCBYTE,&DMA0CTL
                                            ; Rpt, inc src, byte-byte

Main        bis.b   #UCTR+UCTXSTT,&UCB0CTL1 ; Transmitter, Send Start Condition
            bis.w   #DMAEN,&DMA0CTL         ; Enable DMA for consecutive Xfers
            mov.b   #010h,&UCB0TXBUF        ; Write DAC control
            bis.w   #LPM0+GIE,SR            ; Enter LPM0
            nop                             ; Required for debug
;-------------------------------------------------------------------------------
Sine_Tab;   16 Point 16-bit Sine Table
;-------------------------------------------------------------------------------
            DB      0FFh                    ; MSB Word 0
            DB      0FFh                    ; LSB
            DB      0F6h                    ; MSB Word 1
            DB      040h                    ; LSB
            DB      0DAh                    ; MSB Word 2
            DB      081h                    ; LSB
            DB      0B0h                    ; MSB Word 3
            DB      0FAh                    ; LSB
            DB      07Fh                    ; MSB Word 4
            DB      0FFh                    ; LSB
            DB      04Fh                    ; MSB Word 5
            DB      003h                    ; LSB
            DB      025h                    ; MSB Word 6
            DB      07Ch                    ; LSB
            DB      009h                    ; MSB Word 7
            DB      0BDh                    ; LSB
            DB      000h                    ; MSB Word 8
            DB      000h                    ; LSB
            DB      009h                    ; MSB Word 9
            DB      0BDh                    ; LSB
            DB      025h                    ; MSB Word 10
            DB      07Ch                    ; LSB
            DB      04Fh                    ; MSB Word 11
            DB      003h                    ; LSB
            DB      07Fh                    ; MSB Word 12
            DB      0FEh                    ; LSB
            DB      0B0h                    ; MSB Word 13
            DB      0FAh                    ; LSB
            DB      0DAh                    ; MSB Word 14
            DB      081h                    ; LSB
            DB      0F6h                    ; MSB Word 15
            DB      040h                    ; LSB
;-------------------------------------------------------------------------------
            COMMON  INTVEC                  ; Interrupt Vectors
;-------------------------------------------------------------------------------
            ORG     RESET_VECTOR            ; POR, ext. Reset, Watchdog
            DW      RESET
            END
